/////////////////////////////////////////////////////////////////////////////////
// Company       : 武汉芯路恒科技有限公司
//                 http://xiaomeige.taobao.com
// Web           : http://www.corecourse.cn
// 
// Create Date   : 2021/07/22 00:00:00
// Module Name   : ad9226_sdram_usb
// Description   : ADC采集数据，SDRAM缓存，uart上传
// 
// Dependencies  : 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
/////////////////////////////////////////////////////////////////////////////////
module AC620_AD9226_sdram_uart(
	clk,
	reset_n,
	//LED
	led,

	//ADC
	ad_in1,
	ad_in2,
	ad_clk1,
	ad_clk2,
	
	//sdram control
	sdram_clk,
	sdram_cke,
	sdram_cs_n,
	sdram_we_n,
	sdram_cas_n,
	sdram_ras_n,
	sdram_dqm,
	sdram_ba,
	sdram_addr,
	sdram_dq,
	
	uart_rx,
	uart_tx
);

	input clk;
	input reset_n;
	
	//LED
	output [1:0]led;

	//ADC
	input [11:0]ad_in1;
	input [11:0]ad_in2;
	
	input	uart_rx;
	
	output ad_clk1;
	output ad_clk2;
	
	//sdram Interface
	output sdram_clk;
	output sdram_cke;
	output sdram_cs_n;
	output sdram_we_n;
	output sdram_cas_n;
	output sdram_ras_n;
	output [1:0]sdram_dqm;
	output [1:0]sdram_ba;
	output [12:0]sdram_addr;
	inout [15:0]sdram_dq;
	
	output uart_tx;

	reg start_sample_r1;
	reg start_sample_r2;
	

	
	//锁相环时钟输出，给外部需要50M时钟工作的模块提供时钟， 
	wire clk50m; 
	wire clk_sdr_ctrl;
	wire pll_locked;
	
	wire [7:0]cmd_addr;
	wire [31:0]cmd_data;
	wire cmdvalid;
	
	wire [15:0]ad_out;
	wire ad_out_valid;
	
	wire sdram_init_done;
	
	wire wrfifo_clr;
	wire wrfifo_full;
	
	wire ad_sample_en;
	
	wire rdfifo_clr;
	wire rdfifo_empty;
	wire rdfifo_rden;
	wire [15:0]rdfifo_dout;
	

	wire inout_switch;    
	//0: read由pc向FPGA下发指令   1:write由FPGA向fx2芯片继而向pc上传数据
	wire rw_switch;
	
	wire start_sample;
	wire [31:0]set_sample_num;
	wire uart_tx_done;

	wire  wrfifo_wren;
	wire  uart_send_en;
	wire [7:0]uart_tx_data;

	assign ad_clk1 = clk50m;
	assign ad_clk2 = clk50m;
		
	//led[0] 锁相环锁定信号输出，为高，说明锁相环工作正常，时钟正常
	//led[1] sdram初始化完成标识信号，为高，说明sdram已经正常完成初始化
	assign led = {sdram_init_done,pll_locked};
	
	pll pll(
		.inclk0(clk),
		.c0(clk_sdr_ctrl),
		.c1(sdram_clk),
		.c2(clk50m),
		.locked(pll_locked)
	);
	
	wire [7:0]data_byte;
	wire rx_done;
	wire tx_done;
	
	parameter uart_baud_set = 3'd4; //默认115200bps
	uart_byte_rx uart_byte_rx_0(
		.clk(clk50m),
		.reset_n(reset_n),
		
		.baud_set(uart_baud_set),
		.uart_rx(uart_rx),
		
		.data_byte(data_byte),
		.rx_done(rx_done)
);	

	uart_byte_tx uart_byte_tx_0(
		.clk(clk50m),
		.reset_n(reset_n),
		
		.data_byte(uart_tx_data),
		.send_en(uart_send_en),
		.baud_set(uart_baud_set),
		
		.uart_tx(uart_tx),
		.tx_done(tx_done),
		.uart_state() 
);

	state_ctrl state_ctrl_0(
		.clk(clk50m),
		.reset_n(reset_n),
		
		.start_sample(start_sample),
		.set_sample_num(set_sample_num),//16位计数，最大65535，够不够用待定
		.ad_sample_en(ad_sample_en),
		.sdram_init_done(reset_n),
		.uart_tx_done(tx_done),
		.rdfifo_empty(rdfifo_empty),
		.rdfifo_dout(rdfifo_dout),
		.wrfifo_full(wrfifo_full),
		//wrfifo_clr向外打三拍输出，保证wrfifo的清零信号的生效节拍数
		.wrfifo_clr(wrfifo_clr),
		.wrfifo_wren(wrfifo_wren),
		.rdfifo_clr(rdfifo_clr),
		.rdfifo_rden(rdfifo_rden),
		.uart_send_en(uart_send_en),
		.uart_tx_data(uart_tx_data)
	);

//下方模块对接收的信号进行解析，输出地址、数据、有效，然后通过地址判断这个数据是采样起始信号，采样数量，还是采样通道//
	uart_cmd uart_cmd_inst(
		.Clk (clk50m),
		.Reset_n (reset_n),
		.rx_data (data_byte),
		.rx_done (rx_done),
		.address (cmd_addr),
		.data (cmd_data),
		.cmdvalid (cmdvalid)
	);
		
	wire [31:0]set_sample_speed;

	
	wire [1:0]adc_ch_sel;
	uart_cmd_rx uart_cmd_rx_1(
		.clk (clk50m),
		.reset_n (reset_n),
		.adc_ch_sel (adc_ch_sel),
		.set_sample_num (set_sample_num),
		.set_sample_speed(set_sample_speed),
		.start_sample (start_sample),
		.cmdvalid (cmdvalid),
		.cmd_addr (cmd_addr),
		.cmd_data (cmd_data)
	);
	
	wire adc_data_en;
	speed_ctrl speed_ctrl(
		.clk(clk50m),
		.reset_n(reset_n),
		.ad_sample_en(ad_sample_en),
		.adc_data_en(adc_data_en),
		.div_set(set_sample_speed)
	);
	
	always@(posedge clk50m)
	begin
		start_sample_r1<=start_sample;
		start_sample_r2<=start_sample_r1;
	end
	
	//ADC数据选择输出
	ad9226_12bit_to_16bit ad9226_12bit_to_16bit(
		.clk (clk50m),
		.ad_sample_en (ad_sample_en),
		.ch_sel (adc_ch_sel),
		.ad_in1 (ad_in1),
		.ad_in2 (ad_in2),
		.ad_out (ad_out),
		.ad_out_valid (ad_out_valid)
	);
	
	sdram_control_top sdram_control_top(
		.Clk(clk_sdr_ctrl),
		.Rst_n(reset_n),
		.Sd_clk(sdram_clk),
		.Init_done(sdram_init_done),
		
		.Wr_data(ad_out),
		.Wr_en(ad_out_valid && adc_data_en),
		.Wr_addr(0),
		.Wr_max_addr(16*1024*1024-1),
		.Wr_load(wrfifo_clr),
		.Wr_clk(clk50m),
		.Wr_full(wrfifo_full),
		.Wr_use(),
		
		.Rd_data(rdfifo_dout),
		.Rd_en(rdfifo_rden),
		.Rd_addr(0),
		.Rd_max_addr(16*1024*1024-1),
		.Rd_load(rdfifo_clr),
		.Rd_clk(clk50m),
		.Rd_empty(rdfifo_empty),
		.Rd_use(),
		
		.Sa(sdram_addr),
		.Ba(sdram_ba),
		.Cs_n(sdram_cs_n),
		.Cke(sdram_cke),
		.Ras_n(sdram_ras_n),
		.Cas_n(sdram_cas_n),
		.We_n(sdram_we_n),
		.Dq(sdram_dq),
		.Dqm(sdram_dqm)
	);
		
endmodule
